1. Technical Field
The present disclosure relates to integrated circuit (IC) design, and more specifically to timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy.
2. Related Art
A circuit of interest (e.g., an Integrated Circuit (IC)) often contains multiple circuit blocks, with each circuit block being designed to provide a corresponding set of features or functionality. The circuits (or ICs, in the examples here) are divided into such circuit blocks, typically for different teams to develop the blocks in parallel, for easier testing, the nature of circuitry within the blocks (e.g., one block processing digital signals and another block processing analog as well as digital signals) etc.
As an illustration, a System-on-a-Chip (SoC) may contain multiple circuit blocks of (often complex) electronics systems. The individual circuit blocks may contain digital, analog, mixed-signal, radio-frequency (RF) functions, etc. Each block may first be designed and tested independently (using personnel and computing resources suited for the specific blocks), and typically in parallel.
Such independently developed circuit blocks are eventually interconnected into a single integrated circuit (chip) during an integration phase. The design (referred to as “top-level”) of IC formed by such interconnections is again tested for proper interoperability.
Timing analysis of a physical layout of such interconnected design is one of the requirements in the design phases. Such timing analysis generally checks whether a physical layout corresponding to a circuit design operates within the timing constraints necessitated by factors such as desired operation frequency, manufacturing technology, etc. As is well known, a physical layout represents the structure of individual cells/components in corresponding positions and the interconnecting paths with lengths/material, etc., to correspond to the positions of the components.
Models of circuit blocks are often used in timing analysis. A model of a circuit block (referred to often as a design model) is generally a representation, in the form of corresponding set of data, of a desired set of parameters of the circuit block. Timing analysis (noted above) may be performed consistent with the extent of information stored in the models.
For example, in one approach referred to as a black box model used during integration testing), only the input/output ports/nodes are present, and for each boundary timing arc (between an input port and an output port, between an input port and a clock port, or between an output port and a clock port), corresponding timing information may be maintained. The timing information may include delay, setup and hold timing requirements, etc., for the timing arcs.
In another approach referred to as an unabstracted model, the actual physical layout (complete circuit information) is itself used (for all the cells) as a basis for the timing analysis in the integration testing).
In yet another approach referred to as an interface timing model, peripheral circuitry close to the I/O ports/nodes (for example, leading up to a first clocked element in the signal path, and generally termed boundary information), is included in the model. Thus, an interface timing model may contain a physical and electrical copy of circuitry in the peripheral portions (connected to the ports) of the circuit block, but reduced so that it only includes data that may be required when performing top-level integration and verification.
It may be appreciated that each of the approaches above may have associated benefits and deficiencies. For example, the black box model may be computationally efficient and require only a small memory, but may be less accurate than a desired level due to the limited information provided within the model. On the other extreme, the unabstracted models may require substantially more resources, but be accurate. The interface timing model provides benefits and deficiencies in between the two extremes.
Several features of the present invention provide for a better balance of resource requirements and accuracy.